A High Power Density Chip-on-Chip Gan-based Module with Ultra-Low Parasitic Inductance
ID：77
Submission ID：126 View Protection：ATTENDEE
Updated Time：2021-07-21 20:05:55 Hits：640
Oral Presentation
Start Time：2021-08-27 16:00 （Asia/Shanghai）
Duration：15min
Session：[Room1] Oral Session 1 » [S3&S4] WBG Device Applications, Package Design & Analysis
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Abstract
A 650V/120A rated half-bridge chip-on-chip GaN module has been proposed in this paper. The chip-on-chip structure allows to distribute decoupling capacitors close to each device, which can equalize the dynamic turn-on current of parallel devices and reduce the drain-source voltage overshoot. The effect of parasitic inductance on parallel devices is analyzed and optimized. By double-sided cooling, the module shows good thermal performance.
Keywords
GaN,modular
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