The voltage spikes generated by the turn-off of the high-speed switches can easily drive the devices into an avalanche mode and even failure. In order to study the silicon carbide (SiC) MOSFET’s avalanche limit of a single device and the influence of electrical parameters of paralleled devices, an unclamped inductance switching (UIS) test platform for single and paralleled SiC MOSFETs is set up. This paper summarizes the single-pulse avalanche limit of single MOSFET under different inductances through experiments. In addition, the characteristics of parallel connected MOSFETs under different electrical parameters are also analyzed, and the main factors that affect the avalanche failure are shown.
 

silicon carbide MOSFET,unclamped inductance switching,single-pulse avalanche