Comparison Study of Parasitic Inductance, Capacitance and Thermal Resistance for Various SiC Packaging Structures
ID:109
Submission ID:29 View Protection:ATTENDEE
Updated Time:2021-07-21 20:06:15 Hits:682
Oral Presentation
Start Time:2021-08-27 15:30 (Asia/Shanghai)
Duration:15min
Session:[Room1] Oral Session 1 » [S3&S4] WBG Device Applications, Package Design & Analysis
No files
Abstract
Parasitic parameters of packaging structure can affect the performance of silicon carbide (SiC) devices. Previous researches on SiC power modules lack a comprehensive comparison of different kinds of packaging structures. In this paper, six kinds of power modules are designed under the same standard, and their parasitic inductance, parasitic capacitance, and thermal resistance are extracted by finite element simulation for comparison. According to the result, the double-side-cooling structure has the smallest thermal resistance. The chip-on-chip structure shows extremely small parasitic inductance and capacitance, but this structure is complex thus the manufacturing technique and reliability should be considered. The full-shielding structure has extremely small parasitic capacitance and medial parasitic inductance, while its thermal resistance is larger than other structures. The rest three structures show mediocre performance.
Keywords
SiC,packaging,thermal resistance,parasitic inductance,parasitic capacitance
Comment submit